Volumetric Imaging for Semiconductor Technology Advancement

Project scope and motivation

The project addresses a metrology gap: routine 3D characterisation of buried device structures is too slow for modern chip development. Gate-all-around nanosheets and advanced 3D packaging cannot be inspected with surface tools. Current 3D tomography requires 60–120 projections and up to 48 hours per sample. VISTA-3D combines sparse-data reconstruction with industrial imaging to target a validated TRL 4 prototype within 24 months.

Research and development

VISTA-3D develops three innovations: a physics-informed sparse-view reconstruction algorithm, an automated fiducial-free tilt-series alignment method, and an integrated software prototype usable by process engineers. R&D includes synthetic and experimental datasets, paired sparse and full tilt-series of FinFET and GAA nanosheets, benchmarking against conventional reconstructions, and patent filings.

Broader perspective and impact

The project boosts resource efficiency by accelerating yield ramp and reducing defective wafers. It strengthens the Dutch high-tech ecosystem and positions the Netherlands in AI-accelerated electron tomography. Results benefit fabs, research labs, and SMEs, with dissemination via publications, an open dataset, conference presentations, and pilot engagements with partners including imec, Nexperia, and TNO.