Holland High Tech Holland High Tech
Smart Connect

New environmentally friendly generic approach for advanced die connection in Chip Packaging

As part of the Advanced Chip Packaging program, Smart Connect will develop an innovative, generic interconnect technology for semiconductor chips. This key technology will enable the Dutch chip industry to gain a competitive edge in the application of the upcoming generation of advanced photonic, high-power, and high-frequency devices. This initiative addresses the Netherlands' and Europe's desire for independence from China and the US in the field of semiconductor technology.

Good contact and heat dissipation are crucial

In the field of power electronics, so-called wide-bandgap semiconductors such as SiC are rapidly gaining ground due to their superior performance compared to their traditional Si-based counterparts. The higher switching frequencies and power densities of these materials place high demands on the thermal management and mechanical reliability of the semiconductor chip and its package, especially because these chips are often used for critical applications under harsh conditions. For long-term optimal performance, the heat generated by the active part of the chip must be dissipated as efficiently as possible to the underlying substrate in the chip package.

Porous copper films as a solution

A recently developed process can produce nanostructured porous copper films using electrodeposition. Due to the rapid diffusion of material, these structures can achieve a very strong bonding between two elements. Smart Connect investigates which film structure achieves an optimal bonding and thermally conductive connection between a semiconductor chip and its underlying substrate. The goal is to develop an optimal generic interconnect technology for both the current generation of Si-based chips and for the emerging generation of chips based on heterogeneous engineered wafers.

Cooperation to reach the goal

In Smart Connect, a consortium consisting of Radboud University Nijmegen, TNO, and Coolsem Technologies is collaborating to develop an innovative chip interconnect technology. Radboud University is developing an innovative diffusion-driven chip interconnect method based on nano-textured porous copper films. Coolsem Technologies is developing Advanced Engineered Substrates (AES) on which the next generation of photonic, high-power, and high-frequency chips will be produced. Finally, TNO is developing the precise thermal measurement methods needed to monitor the progress made with the bonding technology and the AES, thus guiding the next steps in the research.

Facts & figures
  • Scheme: PPS-I Strategische Programma's
  • Programme: Advanced Chip Packaging | 2025-2027
  • Total budgeted project costs: € 869.777,00
  • Project start date: 1 April 2026
  • Project end date: 28 February 2029
Project managers
Project consortium
Radboud Universiteit TNO Coolsem Technologies
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